-- Main sumador con registros

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.pak_sumador.all;

entity main_regs is
port(clk,rst: in std_logic;
	 p,q: in std_logic_vector(7 downto 0);
     a,b: in std_logic_vector(7 downto 0);
     exp: out std_logic_vector(7 downto 0);
     mantisa: out std_logic_vector(7 downto 0));
end main_regs;

architecture behavior2 of main_regs is
signal rest_dif: std_logic_vector(7 downto 0);
signal rest_max: std_logic_vector(7 downto 0);
signal rest_sel: std_logic;
signal sel_menor_exp: std_logic_vector(7 downto 0);
signal sel_mayor_exp: std_logic_vector(7 downto 0);
signal despld_out: std_logic_vector(7 downto 0);
signal sumar_out: std_logic_vector(7 downto 0);
signal cont_out: std_logic_vector(7 downto 0);
signal acu1_out: std_logic_vector(7 downto 0);
signal acu2_out: std_logic_vector(7 downto 0);
signal acu3_out: std_logic_vector(7 downto 0);
signal acu4_out: std_logic_vector(7 downto 0);
signal acu5_out: std_logic_vector(7 downto 0);
signal acu6_out: std_logic_vector(7 downto 0);
signal acu7_out: std_logic_vector(7 downto 0);
signal acu8_out: std_logic_vector(7 downto 0);
signal despli_out: std_logic_vector(7 downto 0);
signal rest_exp2_out: std_logic_vector(7 downto 0);
begin
rest_exp1: restador port map(p,q,rest_dif,rest_max,rest_sel);
selec: selector port map(a,b,rest_sel,sel_menor_exp,sel_mayor_exp);
despld: desplazadord port map(sel_menor_exp,rest_dif,despld_out);
acu1: acum port map(rst,clk,rest_max,acu1_out); -- max
acu2: acum port map(rst,clk,despld_out,acu2_out); -- desplazador
acu3: acum port map(rst,clk,sel_mayor_exp,acu3_out); -- selector mayor exponente
sum: sumar port map(acu2_out,acu3_out,sumar_out);
acu4: acum port map(rst,clk,acu1_out,acu4_out);
acu5: acum port map(rst,clk,sumar_out,acu5_out);
cont: contador port map(acu5_out,cont_out);
despli: desplazadori port map(acu5_out,cont_out,despli_out);
acu6: acum port map(rst,clk,acu4_out,acu6_out); -- max
acu7: acum port map(rst,clk,cont_out,acu7_out); -- contador
acu8: acum port map(rst,clk,despli_out,acu8_out);
rest_exp2: restador2 port map(acu6_out,acu7_out,rest_exp2_out);
acu9: acum port map(rst,clk,rest_exp2_out,exp);
acu10: acum port map(rst,clk,acu8_out,mantisa);
end behavior2;
